1. Field of the Invention
This invention relates generally to digital communications, and more specifically to phase selection circuits.
2. Description of the Prior Art
For many applications in integrated circuit (IC) design, signal source such as a voltage controlled oscillator (VCO) is utilized to generate a multi-phase clock signal. A phase selection circuit is typically utilized in conjunction with signal source to select desired phases. Conventional phase selection circuits suffer from various shortcomings, however, including but not limited to, bandwidth, mismatch and/or glitching problems. For example, one known phase selection circuit utilizes several stages of multiplexing gates for selecting a desired output phase signal, with each gate being enabled by a select input signal. The signals applied to the phase selection circuit must pass through several stages of gates. As the signals pass through each stage of gates, the amount of mismatch caused by the time delay between phases increases. Moreover, the amount of mismatch increases as the number of phases increases. Another problem associated with multi-stage phase selection circuits is that the resultant output phase signal is subject to perturbation or glitching when the select input signals for the gates are changed. This can be improved somewhat by arranging the select input signals so that the select coding changes from a binary to a Gray code (i.e., a binary code in which sequential numbers are represented by binary expressions each of which differs from the preceding expression by one place only). While utilizing a Gray code helps, perturbation or glitching of the output phase signal remains problematic, particularly when the select inputs for the gates are changed asynchronously.
Another conventional phase selection approach utilizes tristateable multiplexors for selecting a desired output phase signal, with each multiplexor enabled by a select input signal. All of the phases applied to a tristateable phase selection circuit are shorted together through tristateable buffers. This approach suffers from various shortcomings, however, including limited bandwidth availability caused by excessive loading of all of the disabled drivers connected to an output node. Additionally, perturbation or glitching at the output phase signal remains problematic.
What is needed therefore is an apparatus and method for phase selection which provides for maximum bandwidth capability while minimizing phase mismatch and glitching at the output phase signal.